How To Build Resilience Into Chips

Heterogeneous designs, customization, and increasing complexity open doors for hardware errors.

From Lab To Fab: Increasing Pressure To Fuse IC Processes

Efforts mount to connect metrology, test, and inspection across both worlds as chips become more complex and expensive.

Using AI To Improve Metrology Tooling

Virtual metrology shows benefits in limited trials, but much work still needs to be done.

True 3D Is Much Tougher Than 2.5D

While terms often are used interchangeably, they are very different technologies with different challenges.

Metrology Strategies For 2nm Processes

Tools become more specific for Si/SiGe stacks, 3D NAND, and bonded wafer pairs.

How Chip Engineers Plan To Use AI

Checks, balances, and unknowns for AI/ML in semiconductor design.

True 3D-IC Problems

Stacking logic requires solving some hidden issues; concerns about thermal dissipation may be the least of them.

New Standards Push Co-Packaged Optics

Speed, density, distance, and heat all need to be considered; pluggables still have a future.

IC Security Issues Grow, Solutions Lag

Signing off on hardware security may involve lifetime updates; AI adds unknowns that are difficult to trace.

Assist Layers: The Unsung Heroes Of EUV Lithography

Various materials work in concert with the scanner, photoresist and photomasks to make EUV lithography work.